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this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. rev. 4.0 february 2000 1/24 STV9432TA 100mhz osd for monitor including beam currents & video timing analyzer ? multifunction osd for monitor ? includes facilities for cut-off volt- ages monitoring: - three 8 bits adc inputs - adc trigger during retrace time of a programmed line ? includes facilities for screen size & centering auto setup - hs, vs, video timing measurements ? 100mhz max. pixel clock, available for any line frequency between 15 and 140 khz ? 12 x 18 character rom font includes: - 240 monocolor characters - 16 multicolor characters ? character flashing ? up to 1k characters text display ? ultra high frequency pll for jitter- free display ? flexible display: - any character width and height - anywhere in the screen ? single byte character codes and color look-up table for easy pro- gramming and fast access ? character flip operations ? wide display window allows pattern generation for factory adjustments ?i 2 c bus mcu interface description connected to a host mcu via a serial i 2 c bus, the STV9432TA is a multifunction slave peripheral device integrating the following blocks: - on-screen display. it includes a mask pro- grammable rom that holds the custom character font, a 1kbytes ram that stores the code strings of the different lines of text to be displayed, and a set of registers to program char- acter sizes and colors. a built-in digital pll, oper- ating at very high frequency, provides an accurate display without visible jitter for a wide line fre- quency range from 15 to 140 khz. - cut-off monitoring circuitry includes 3 x 8 bits adcs and a programmable adc sampling trigger. it gives the possibility to measure the three beam currents, during the horizontal flyback, at a given line in the frame, provided that the three adc inputs are connected to a beam current sensing circuitry. the values are stored in three beam current registers, and available for mcu read. - video timing analyzer. using the horizontal sync, vertical sync, horizontal flyback, and "video active" inputs, a set of counters provide the differ- ent timing measurements necessary to analyze the current video timing characteristics to make the automatic set-up of screen size and centering. the measurements are initialized on the same programmable trigger line than in the above cut-off monitoring circuitry pin connections sdip24 (plastic package) order code: STV9432TA 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 24 23 22 21 rci gci bci adcref agnd test filter hfly av dv dd dv ss rout gout bout fblk sda scl hs vs xti xto ov ss ov dd av dd 1
STV9432TA 2/24 1 - pin description pin number symbol type description 1 filter i/o pll filter 2 agnd power analog ground 3 sda i/o i 2 c bus serial data 4 scl i i 2 c bus serial clock 5 hs i horizontal sync input 6 vs i vertical sync input 7 hfly i horizontal flyback input 8 av i active video input 9 dv dd power digital +5v power supply 10 dv ss power digital ground 11 xti i crystal oscillator input 12 xto o crystal oscillator output 13 ov ss power ground for the rgb outputs 14 rout o red output 15 gout o green output 16 bout o blue output 17 fblk o fast blanking output 18 ov dd power +5v supply for the rgb outputs 19 av dd power analog +5v power supply 20 bci i blue beam current input 21 gci i green beam current input 22 rci i red beam current input 23 adcref i/o adc reference voltage pin 24 test i/o pin must be connected to ground 2
STV9432TA 3/24 2 - block diagram 3 - absolute maximum ratings symbol parameter value unit av dd , dv dd , ov dd supply voltage -0.3, +6.0 v v in input voltage v ss - 0.3, v dd + 0.3 v t oper operating temperature 0, +70 o c t stg storage temperature -40, +125 o c oscillator pll voltage regulator power-on reset i 2 c bus interface character font rom 1k bytes ram 18 test filter 5 hfly 4 vs timings analyzer beam current measure 3 6 22 21 hs av rci gci bci 20 adcref 3.3v 13 9 10 11 12 rout gout bout fblk display controller 1 2 sda scl 7 dv dd 8 dv ss 19 agnd av dd 17 16 15 14 23 xti xto ov ss ov dd STV9432TA 24 2
STV9432TA 4/24 4 - electrical characteristics (v dd = 5v, v ss = 0v, gnd = 0v, t a = 0 to 70 o , unless otherwise specified) symbol parameter min. typ. max. unit supply av dd , dv dd , ov dd supply voltage 4.75 5 5.25 v ai dd + di dd + oi dd analog and digital supply current - - 150 ma inputs (scl, sda) v il input low voltage 0.8 v v ih input high voltage 2.4 v i il input leakage current -1 +1 a inputs (hs, vs, av, hfly) v il input low voltage 0.8 v v ih input high voltage hs, vs, av hfly 2.4 3.6 v v hyst schmidt trigger hysteresis 0.4 v i pu pull-up source current (v in = 0v) 100 a hsin horizontal synchro input range 15 140 khz outputs (sda open drain) v ol output low voltage (i ol = 3ma) 0 0.4 v outputs (r, g, b, fblk) v ol output low voltage (i ol = 3ma) 0 0.4 v v oh output high voltage (i oh = 3ma) 0.8v dd v dd v oscillator (xti, xto) i il xti input source current (v in = 0v) 3 15 a i ih xti input sink current (v in = v dd )3 15a v il xti input low voltage 1.4 v v ih xti input high voltage 0.7v dd v v ol xti output low voltage (i ol = 3ma) 0 0.4 v v oh xti output high voltage (i oh = 3ma) 0.8v dd v dd v adcref v ref output voltage reference 3.3 v power-on reset dv ddth supply threshold level 3.6 v 8 bits adc inputs (rci gci bci) v in input voltage 0 v adcref v z in input impedance 100 k v off input offset voltage 3 lsb i leak input leakage current 0 50 a ile integral linearity error (note 2) -2 +2 lsb dle differential linearity error (note 2) -0.5 +0.5 lsb w 2
STV9432TA 5/24 5 - timings note 1: these parameters are not tested on each unit. they are measured during our internal qualification procedure which inclu des char- acterization on batches comming from corners of our processes and also temperature characterization note 2 : the adc measurements are dependant on the noise. the test is done by correlation in order to screen out marginal devic es. note 3 : t htim = 3t osc : 40. figure 1. symbol parameter min. typ. max. unit oscillator f osc clock frequency 8 mhz f pxl pixel frequency 100 mhz r, g, b, fblk (c load = 30pf) t r rise time (see note 1) 5 ns t f fall time (see note 1) 5 ns t skew skew between r, g, b, fblk 5 ns i 2 c interface: sda and scl (see figure 1 ) f scl scl clock frequency 0 400 khz t buf time the bus must be free between 2 access 500 ns t hds hold time for start condition 500 ns t sup set up time for stop condition 500 ns t low the low period of clock 400 ns t high the high period of clock 400 ns t hdat hold time data 0 ns t sudat set up time data 500 ns t f fall time of sda 20 ns t r rise time of both scl and sda depend on the pull-up resistor and the load capacitance analyzer (hs, hfly, av) t hlow low pulse width (see note 3) 2 4091 t htim t hhigh high pulse width (see note 3) 2 4091 t htim hs max max hs frequency hfly analyzer (vs) t vlow low pulse width 2 4091 lines t vhigh high pulse width 2 4091 lines sda scl stop start data t buf t hdat t hds t sup t high t low stop t sudat 2
STV9432TA 6/24 6 - serial interface the 2-wires serial interface is an i 2 c interface. to be connected to the i 2 c bus, a device must own its slave address; the slave address of the STV9432TA is ba (in hexadecimal). 6.1 - data transfer in write mode the host mcu can write data into the STV9432TA registers or ram. to write data into the stva9432ta after a start, the mcu must send ( figure 2 ): - first, the i 2 c address slave byte with a low level for the r/w bit, - the two bytes of the internal address where the mcu wants to write data(s), - the successive bytes of data(s). all bytes are sent msb bit first and the write data transfer is ended with a stop. 6.2 - data transfer in read mode the host mcu can read data from the STV9432TA registers, ram or rom. to read data from the STV9432TA ( figure 3 ), the mcu must send 2 different i 2 c sequences. the first one includes the i 2 c slave address byte with r/w bit at low level and the 2 internal address bytes. the second one includes the i 2 c slave address byte with r/w bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence. figure 2. i 2 c write operation figure 3. i 2 c read operation a6 a5 a4 a3 a2 a1 a0 rw 1011101 scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 - - a13 a12 a11 a10 a9 a8 i 2 c slave address ack lsb address ack msb address ack start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack data byte 1 data byte 2 ack data byte n stop scl sda scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 i 2 c slave address ack lsb address ack msb address ack start -- a13 a12 a10 a10 a9 a8 stop scl sda r/w d7 d6 d5 d4 d3 d2 d1 d0 i 2 c slave address ack ack data byte n ack start d7 d6 d5 d4 d3 d2 d1 d0 stop data byte 1 * 2
STV9432TA 7/24 6.3 - addressing space 6.3.1 - general mapping STV9432TA registers, ram and rom are mapped in a 32k address space. the mapping is: important notice: all 16 bits datas are mapped lsb byte at lower address and msb byte at higher ad- dress. C example: h1 12 bits register: @4000: 8 lsb bits - @4001: 4 msb bits. C descriptors must also be written to ram lsb byte first. 6.3.2 - i 2 c registers mapping 0000 03ff 1024 bytes ram descriptors and character codes 0400 07ff empty space 0800 3fff character generator rom 4000 403f internal registers 4040 7fff empty space 4000 h1 lsb 4022 color 2 4001 h1 msb 4023 color 3 4002 h2 lsb 4024 color 4 4003 h2 msb 4025 color 5 4004 h3 lsb 4026 color 6 4005 h3 msb 4027 color 7 4006 h4 lsb 4028 color 8 4007 h4 msb 4029 color 9 4008 h5 lsb 402a color 10 4009 h5 msb 402b color 11 400a h6 lsb 402c color 12 400b h6 msb 402d color 13 400c v1 lsb 402e color 14 400d v1 msb 402f color 15 400e v2 lsb 4030 line duration 400f v2 msb 4031 top margin 4010 v3 lsb 4032 horizontal delay 4011 v3 msb 4033 character height 4012 rci 4034 display control 4013 gci 4035 locking time constant 4014 bci 4036 capture time constant 4015 sbn 4037 initial pixel period 4016 timg 4038-403e reserved 4017-401f reserved 403f rst 4020 color 0 4040-7fff reserved 4021 color 1
STV9432TA 8/24 7 - timing analyzer 7.1 - video horizontal timings all horizontal timing measurements use a 106.7mhz clock. this clock is made from the internal oscillator: f htim = 40f osc : 3. these twelve bits read-only registers read time measurements, given in t htim units. they hold the value of the last measurement that was initiated by i 2 c command (see timg register). figure 4. h1 register : h sync to active video, min of c to a h2 register : active video to h sync, min of b to c' h3 register : line period, c to c' h4 register : h fly to h sync, e to c h5 register : h sync to h fly, c to e' h6 register : h fly pulse, e to f 7.2 - video vertical timings these twelve bits read-only registers read time measurements, given in number of scan lines. they hold the value of the last measurement that was initiated by i 2 c command (see timg register). figure 5. av hs hfly b l' f' l f aa' k' k ee' 4000 h1.7 h1.6 h1.5 h1.4 h1.3 h1.2 h1.1 h1.0 4001 - - - - h1.11 h1.10 h1.9 h1.8 4002 h2.7 h2.6 h2.5 h2.4 h2.3 h2.2 h2.1 h2.0 4003 - - - - h2.11 h2.10 h2.9 h2.8 4004 h3.7 h3.6 h3.5 h3.4 h3.3 h3.2 h3.1 h3.0 4005 - - - - h3.11 h3.10 h3.9 h3.8 4006 h4.7 h4.6 h4.5 h4.4 h4.3 h4.2 h4.1 h4.0 4007 - - - - h4.11 h4.10 h4.9 h4.8 4008 h5.7 h5.6 h5.5 h5.4 h5.3 h5.2 h5.1 h5.0 4009 - - - - h5.11 h5.10 h5.9 h5.8 400a h6.7 h6.6 h6.5 h6.4 h6.3 h6.2 h6.1 h6.0 400b - - - - h6.11 h6.10 h6.9 h6.8 av vs b l' l aa' k' k 3
STV9432TA 9/24 v1 register: v sync to active video, min. of k to a v2 register : active video to v sync, min. of b to k' v3 register : number of lines per frame, k to k'7 7.3 - timing analysis trigger the timing analysis is performed according to the setting of sbn and timg registers : 7.3.1 - sbn register this 8 bits register holds the "sampling bloc" number. the sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or beam currents. the reset value of this register is zero, must be programmed at a minimum value of 1 for correct operation. 7.3.2 - timg register this 8 bits register holds the following parameters: to initiate a timing analysis cycle: - program the sampling bloc number in the sbn register, - program the timg register, with: "select" bit =1, "nfr" bits specify the number of measurement frames (h1, h2, v1, v2), "stm" bit = 1 (start measurement). as soon as the measurement cycle is finished, the "stm" bit is automatically reset by the device. after a timing analysis cycle, reading a zero in stm bit of timg register means that the measurement is com- pleted and the mcu may read the results in hi and vi registers. the reset value of this register is 0. 400c v1.7 v1.6 v1.5 v1.4 v1.3 v1.2 v1.1 v1.0 400d - - - - v1.11 v1.10 v1.9 v1.8 400e v2.7 v2.6 v2.5 v2.4 v2.3 v2.2 v2.1 v2.0 400f - - - - v2.11 v2.10 v2.9 v2.8 4010 v3.7 v3.6 v3.5 v3.4 v3.3 v3.2 v3.1 v3.0 4011 - - - - v3.11 v3.10 v3.9 v3.8 4015 sbn7 sbn6 sbn5 sbn4 sbn3 sbn2 sbn1 sbn0 4016 stm nfr1 nfr0 adcdly3 adcdly2 adcdly1 0 select stm : start measurement bit. this bit has to be forced to 1 by i 2 c to start the measurement sequence, depending on the measurement selection bit. when measurement is com- pleted the ic will reset this bit to 0. nfr [1:0] : nfr number of measurement frames, 1 to 4 frames adcdly[3:1] : cut-off beam current adc sampling delay time: 0 to 15 x t osc , by t osc steps select : selection of beam current measurement (0) or timing measurement (1) 3
STV9432TA 10/24 figure 6. video timing measurement sequence - select bit = 1 (timg register, bit 0) i 2 c set stm bit (timg register) wait for acknowledge bit wait for rising edge of vs acquisition of h3, h4, h5, h6 wait for 4*sbn rising edges of hs after nfr+1 frames, reset stm bit measures v3 measures h2 at every line during nfr+1 frames. after nfr+1 frames, h2 holds the min.value measures h1 at every line during nfr+1 frames. after nfr+1 frames, h1 holds the min.value measures v2 during nfr+1 and keeps the min. value measures v1 during nfr+1 and keeps the min. value 3
STV9432TA 11/24 8 - beam currents measurement 8.1 - beam current measurement registers the beam current measurement circuitry uses three a to d converters, sampled at f osc frequency. these three 8 bits registers read the values of the last beam currents measurement, initiated by i 2 c com- mand (see timg register). rci register : red beam current input gci register : green beam current input bci register : blue beam current input 8.2 - beam current measurement trigger the beam currents measurement is performed according to the setting of sbn and timg registers : 8.2.1 - sbn register this 8 bits register holds the "sampling bloc" number. the sampling bloc is a set of 4 consecutive scan lines, the first of which is used for sampling the video timings or beam currents. the reset value of this register is 0. 8.2.2 - timg register this 8 bits register holds the following parameters: to initiate a beam currents measurement cycle: - program the sampling bloc number in the sbn register, - program the timg register, with: "select" bit = 0, "adcdly" bits specify the sampling time during hfly, "stm" bit = 1 (start measurement). as soon as the measurement cycle is finished, the "stm" bit is automatically reset by the device. af- ter a beam currents measurement cycle, reading a zero in stm bit of timg register means that the measurement is completed and the mcu may read the results in rci, gci, and bci registers. the reset value of this register is 0. 4012 rci7 rci6 rci5 rci4 rci3 rci2 rci1 rci0 4013 gci7 gci6 gci5 gci4 gci3 gci2 gci1 gci0 4014 bci7 bci6 bci5 bci4 bci3 bci2 bci1 bci0 4015 sbn7 sbn6 sbn5 sbn4 sbn3 sbn2 sbn1 sbn0 4016 stm nfr1 nfr0 adcdly3 adcdly2 adcdly1 0 select stm : start measurement bit. this bit has to be forced to 1 by i 2 c to start the measurement sequence, depending on the measurement selection bit. when measurement is com- pleted the ic will reset this bit to 0. nfr [1:0] : nfr number of measurement frames, 1 to 4 frames adcdly [3:1] : cut-off beam current adc sam- pling delay time: 0 to 14 x t osc , by t osc steps select : selection of beam current mea- surement (0) or timing mea- surement (1) 4
STV9432TA 12/24 figure 7. beam currents measurement sequence - select bit = 0 (timg register, bit 0) i 2 c set stm bit (timg register) wait for acknowledge bit wait for rising edge of vs wait for rising edge of hfly wait for adc dly acquisition of rbc, gbc, bbc reset stm bit wait for 4*sbn rising edges of hs 4
STV9432TA 13/24 9 - software reset register to perform a software i 2 c reset of the device, set the rst bit to one. this bit will be automatically reset by the device. software reset will put all write registers at their default power-on value, and reset all internal logic blocks except the i 2 c bus interface itself. it will not change the ram contents. 10 - on-screen display the STV9432TA on-screen display is able to dis- play any line of characters (character strip) any- where in the screen. character strings are programmed by the mcu in ram via i 2 c bus. character shapes are coded in the internal rom font. character strips may be adjacent or separated by vertical spaces (spacing strips). consequently, one display page is made of a list of character strips and spacing strips. a top margin and a left margin are programmable in dedicated registers. 10.1 - ram programming 10.1.1 - two kinds of data: strip descriptors and character codes an osd screen is made of a number of character and spacing strips. two groups of data make one osd screen: - a strip descriptors list, - text strings - one per character strip. each strip is associated with a 2 bytes strip descriptor. there are two strip descriptors: - the character strip descriptors containing the text string ram address of the character strip, - the spacing strip descriptors which specify the vertical space height. in the example shown in figure 8 on page 13 , the osd screen, is made of 9 strips. in ram, there is: - one list of 9 strip descriptors (size = 9 x 2 bytes = 18 bytes), - 6 text strings, each of them made of the character codes from the line of text. text strings can be programmed anywhere in ram. the descriptor list can be located at 16 dif- ferent addresses in ram. the address is defined in the display control register. it is consequently possible to store up to 16 different pages in ram. the current displayed page is specified in the dis- play control register. it refers to a given page descriptor list. figure 8. display page: list of character and spacing strips 403f - - - - - - - rst selxtal this bit must be set to one in order to operate the oscillator in the external crystal mode. in its zero default state, this bit enables the internal rc mode oscillator. top margin left margin text line number one text line number two text line number three text line number four text line number five text line number six strip 1 : character strip strip 2 : character strip strip 3 : spacing strip strip 4 : character strip strip 5 : spacing strip strip 6 : character strip strip 7 : character strip strip 8 : character strip strip 9 : spacing strip (bottom margin) 5
STV9432TA 14/24 10.1.2 - descriptors spacing character 10.1.3 - code format there are basically 3 kinds of code: - the control codes from 0 to 15 (00h to 0fh), - the rom monochrome character codes from 16 to 255 (10h to ffh), - the two bytes multicolor character codes from 08f0 to 08ff (hex). for code definitions see table 1 . table 1 character and command codes single byte codes 00 to 0f are command codes. single byte codes 10 to ff are monochrome character codes. double byte codes 08f0 to 08ff are multicolor character codes. msb 0 l/ ------ c lsb sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0 l/ : line or character spacing: = 0, spacing descriptor defined as character height (sl[7:0] = 1 to 255 character). = 1, spacing descriptor defined as scan line height (sl[7:0] = 1 to 255 scan lines). sl[7:0] : number of selected height (character or scan lines according l/ ). msb 1 de clu3 clu2 clu1 clu0 c9 c8 c c lsb c7 c6 c5 c4 c3 c2 c1 c0 de : display enable: = 0, r = g = b = 0 and fblk = fbk bit of display control register on the whole strip, = 1, display of the characters. clu[3:0] : active color selection at the begining of the strip. c[9:1] : address of the first character code of the strip. c0 : address 0 must be 0. 0 123456789abcdef 0 col 0 1 col 1 2 col 2 3 col 3 4 col 4 5 col 5 6 col 6 7 col 7 240 monochrome characters 8 multicol 9nop a vflip b hflip c dflip d call e rtn f eof 5
STV9432TA 15/24 figure 9. character font of the STV9432TA 5
STV9432TA 16/24 control codes control codes must be followed by a displayable code, except for rtn & eol. they must not be used twice consecutively without a displayable code between them. the control code call is preceded by an address byte. the control codes are not displayed except if mentioned. codes 0 to 7 (0h to 7h): col0 to col7 codes select 1 byte among 8 within the clut in ram. the block selection is fixed by clu3 bit of the active character descriptor (see table 1 and table 2). code 8 (08h): multicolor character precode, must be followed by a multicolor character number from f0h to ffh. code 9 (09h): nop: no operation is performed, can be used to spare a location in ram for an active control code. codes 10 to 12 (0ah to 0ch): flips: hflip(0bh) horizontal flip code flips horizontaly the following displayable code. vflip(0ah) vertical flip code flips verticaly the following displayable code. dflip(0ch) horizontal & vertical flip code flips horizontaly and verticaly the following displayable code. code 13 (0dh): call, this control code switches the display of the next character to the code address given by the next byte as follows: code 14 (0eh): rtn: return to the call + 1 code location (see note). code 15 (0fh): eol, end of line terminates the display of the cur- rent row. rom character codes codes 16 to 255 (10h to ffh): rom monochrome character codes. the charac- ter shapes are 12x18 pixel matrix described in fig- ure 9 . codes 256 to 272 (f0h to ffh): rom multicolor character codes. they must be preceded by the multicolor pre-code 08h. the character shapes are 12x18 pixel matrix described in figure 9 . 10.2 - osd look-up table color look-up table [clut] is read/write ram table. mapping address is described in chapter 6.3.2 - i2c registers mapping on page 7. the clut is splitted into 2 blocks of 8 bytes. each byte contains foreground and background infor- mations as described below: each block may store a different set of colors. one block of colors may be used for the normal items of the menu while the second block, with brighter colors, may be used for selected items of the menu. the block selection is done by programming bit clu3 of clu[3:0] of the character descriptor (see table 2 ). it remains selected for the whole row. bit clu2, clu1 and clu0 of clu[3:0] of the character descriptor select the active color at the beginning of the row. the active color can be modified along the row, using 8 control codes col0 to col7. each control code (col0 to col7) activates a dedicated color byte in the clut as described in table 2. call code (odd @ ) msb 00001101 address byte (even @ ) lsb a8 a7 a6 a5 a4 a3 a2 a1 a[9:1] : address of the next code to be used (a0 = 0 only even addresses), in low half part of ram. notes: call and rtn code must be used simultaneously. call and rtn codes are displayed as a space character. call and rtn codes must be placed at odd ad- dresses. they may be preceded by a nop to place them at the right position. tra br bg bb fl fr fg fb tra fl br, bg, bb fr, fg, fb : : : : transparent background flashing foreground background color foreground color 5
STV9432TA 17/24 table 2 clut block selection 10.3 - osd control registers line duration (reset value: 20h) top margin (reset value: 30h) clu3 clu[2:0] code name command code (hex) ram @(hex) reset value (hex) 0 col 0 00 @4020 07 1 col 1 01 @4021 16 0 2 col 2 02 @4022 25 3 col 3 03 @4023 34 4 col 4 04 @4024 43 5 col 5 05 @4025 52 6 col 6 06 @4026 61 7 col 7 07 @4027 70 0 col 0 00 @4028 70 1 col 1 01 @4029 61 2 col 2 02 @402a 52 1 3 col 3 03 @402b 43 4 col 4 04 @402c 34 5 col 5 05 @402d 25 6 col 6 06 @402e 16 7 col 7 07 @402f 07 4030 vsp hsp ld6 ld5 ld4 ld3 ld2 ld1 vsp : v-sync active edge selection = 0, falling egde, = 1, rising edge. hsp : hfly active edge selection = 0, rising egde, = 1, falling edge. ld[6:1] : line duration ld0 = 0 ld1 = 2 periods of character one character period is 12 pixels long. 4031 m9 m8 m7 m6 m5 m4 m3 m2 m[9:2] : top margin height from the vsync reference edge. m0 = 0, m1 = 0 m2 = 4 scan lines note : the top margin is displayed before the first strip of descriptor list. it can be black if fbk of display control register is set or transparent if fbk is clear. 5
STV9432TA 18/24 horizontal delay (reset value: 20h) characters height (reset value: 24h) display control (reset value: 00h) locking condition time constant (reset value: 01h) 4032 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 dd[7:0] : horizontal display delay from the hsync reference edge to the 1 st pixel position of the charac- ter strips. unit = 6 pixel periods. minimum value is 08h. first pixel position = [dd[7:0] - 6] x 6 + 54 with dd[7:0] = 0,2,4,6 delay is 54 pixel and with dd[7:0] = 1,3,5 delay is 60 pixel 4033 - - ch5 ch4 ch3 ch2 ch1 ch0 ch[5:0] : height of the character strips in scan lines. for each scan line, the number of the slice which is dis- played is given by: slice-number = scan-line-number = number of the current scan line of the strip. 4034 osd fbk fl1 fl0 p9 p8 p7 p6 scan-line-number x 18 ch[5:0] round ( ) osd : on/off (if 0, r, g, b and fblk outputs are 0). fbk : fast blanking control: = 1, forces fblk pin at "1" outside and inside the osd area. this leads to blank video rgb and to only display osd rgb. = 0, fblk pin is driven according character code for normal display of osd data. fl[1:0] : flashing mode : - 00: no flashing. the character attribute is ignored, - 01: flashing at f f (50% duty cycle), - 10: flashing at 2 f f - 11: flashing at 4 f f note: f f is 128 time vertical frequency. p[9:6] : address of the 1 st descriptor of the current displayed pages. p[13:10] and p[5:0] = 0; up to 16 different pages can be stored in the ram. 4035 fr as2 as1 as0 luk bs2 bs1 bs0 fr : free running; if = 1 pll is disabled and the pixel frequency keeps its last value. as[2:0] : phase constant during locking conditions. bs[2:0] : frequency constant during locking conditions. luk : lock unlock status bit 0 = unlocked pll 1 = locked pll 5
STV9432TA 19/24 capture process time constant (reset value: 24h) initial pixel period (reset value: 06h) 10.4 - osd timings the number of pixel periods is given by the line duration register and is equal to: [ld[6:1] x 2 + 1 ] x 12. (ld[6:1]: value of the line duration register). this value is used to define the horizontal size of the characters. the horizontal left margin is given by the hori- zontal delay register and is equal to: (dd[7:0] -6) x 6 + 54 (dd[7:0]: value of the display delay register). this value is used to define the horizontal position of the characters on the screen. due to internal logic, minimum horizontal delay is fixed at 4.5 characters (54 pixel) when dd is even and inferior or equal to 6, and it is fixed at 5 characters (60 pixel) when dd is odd and inferior or equal to 7. 10.5 - pll the pll function of the STV9432TA provides the internal pixel clock locked on the horizontal syn- chro signal and used by the display processor to generate the r, g, b and fast blanking signals. it is made of 2 plls. the first pll which is analog (see figure 10 ) provides a high frequency that is 40 times the internal oscillator frequency, or 320mhz. this high frequency clock is used by the display controller. the 320mhz frequency is then divided by three. the resulting 106.7mhz clock is used by the video timings analysis block. the second pll, fully digital (see figure 11 ), pro- vides a pixel frequency locked on the horizontal synchro signal. the ratio between the frequencies of these 2 signals is: m = 12 x (ld[6:1] x 2 + 1) where ld[6:1] is the value of the line duration register. figure 10. analog pll figure 11. digital pll 10.5.1 - programming of the pll registers initial pixel period (@4037) this register allows to increase the speed of the pll convergence when the horizontal frequency changes (new graphic standard). the relationship between pp[7:0], ld[6:1], f hsync and f osc is: 4036 len af2 af1 af0 - bf2 bf1 bf0 len : lock enable 0 = r,g,b, fblk are always enabled, 1 = r,g,b,, fblk are enabled only when pll is locked. af[2:0] : phase constant during the capture process. bf[2:0] : frequency constant during the capture process. 4037 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 pp[7:0] : value to initialize the pixel period of the pll. vco 40 filter n ? f os c f osc %d %m algo m ? f h-sync f h-syn c err(n) d(n) 40 ? f osc 40 . f osc 6 . (2 . ld + 1) . f hsync pp[7:] = round ( ) 5
STV9432TA 20/24 locking condition time constant (@ 4035) this register provides the as[2:0] and bs[2:0] constants used by the algo part of the pll (see figure 10 ). these two constants as well as the phase error (err(n)) give the new value (dn) of the high frequency signal division. consequently, as[2:0] and bs[2:0] fix the pixel clock frequency. these two constants are used only in locking con- dition, if the phase error is inferior to a fixed value during at least 4 scan lines. if the phase error becomes superior to the fixed value, the pll is not in locking condition but in capture process. in this case, the algo part of the pll uses the other constants af[2:0] and bf[2:0] from the next regis- ter. capture process time constant (@ 4036) the choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the pll. 10.5.2 - how to choose the time constant value the time response of the pll is given by its char- acteristic equation which is: (x - 1) 2 + ( ) . (x - 1) + = 0 where: [6:1] . 2 a -11 and = 3 . ld[6:1] . 2 b - 19 (ld[6:1] = value of the line duration register, a = value of the 1st time constant, af or as and b = value of the 2 d time constant, bf or bs). as can be seen, the solution depends only on the line duration and the time constants given by the i 2 c registers. if ( ) 2 - 4 and 2 < 4, the pll is sta- ble and its response is as shown in figure 15. if ( ) 2 - 4 , the response of the pll is as shown in figure 13 . in this case the pll is stable if > 0.7 damping coefficient. table 3 gives some good values for a and b con- stants for different values of the line duration. figure 12. time response of the pll/ characteristic equation solutions (with real solutions) figure 13. time response of the pll/ characteristic equation solutions (with complex solutions) table 3 valid time constants examples case of a[2:0] = 1 (001) and b[2:0] = 4 (100) :table meaning: n = no possible capture - no stability, y = pll can lock. ab + b a 3ld = b ab + b 0 3ab C ab + b 0 t pll frequency input frequency f 1 f 0 t f 1 f 0 t pll frequency input frequency f 1 f 0 t f 1 f 0 t b \ a 0 1 2 3 4 5 6 0 yyyy yyyy yyyy yyyn ynnn nnnn nnnn 1 yyyy yyyy yyyy yyyn ynnn nnnn nnnn 2 nyyy yyyy yyyy yyyn ynnn nnnn nnnn 3 nnny yyyy yyyy yyyn ynnn nnnn nnnn 4 nnnn nyyy (1) yyyy yyyn ynnn nnnn nnnn 5 nnnn nnny yyyy yyyn ynnn nnnn nnnn 6 nnnn nnnn nyyy yyyn ynnn nnnn nnnn 7 nnnn nnnn nnny yyyn ynnn nnnn nnnn ld[6:1] 8 16 24 32 valid time constants nyyy 5
STV9432TA 21/24 11 - application diagram figure 14. test 24 adcref 23 rci 22 gci 21 bci 20 avdd 19 ovdd 18 1 filter 2 agnd 3 sda 4 scl 5 hs 6 vs 7 hfly 8 av 9 dvdd 10 dvss 11 xti 12 xto fblk 17 bout 16 gout 15 rout 14 ovss 13 22pf 22pf 1nf 2.2k w 100pf 100nf 22 m f 47 m f vdd +5v gnd 100nf 100nf 100nf 1k w 100pf 1k w 100pf 1k w beam current inputs i2c bus active video fly back pulse vertival sync horizontal sync rgb outputs fast blanking ouput xtal 8 mhz separate path for digitlal gnd 100 m h 100 m h 100 m h 100pf c1 100pf c2 100pf c3 100pf c4 c5 c6 c7 c8 c9 c10 c11 c12 c14 c14 c15 c16 l1 l2 l3 r1 r2 r3 r4 5
STV9432TA 22/24
STV9432TA 23/24 12 - package mechanical data 24 pins - plastic dip (shrink) stand-off a1 b e b1 d 13 12 24 1 f la e1 a2 c e1 e e2 gage plane .015 0,38 e2 e3 e sdip24 dimensions millimeters inches min. typ. max. min. typ. max. a 5.08 0.20 a1 0.51 0.020 a2 3.05 3.30 4.57 0.120 0.130 0.180 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 b1 0.76 1.02 1.14 0.030 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 d 22.61 22.86 23.11 0.890 0.90 0.910 e 7.62 8.64 0.30 0.340 e1 6.10 6.40 6.86 0.240 0.252 0270 e 1.778 0.070 e1 7.62 0.30 e2 10.92 0.430 e3 1.52 0.060 l 2.54 3.30 3.81 0.10 0.130 0.150 6
24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics. ? 2000 stmicroelectronics - all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 7

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